A. Field of the Invention
The present invention relates to a high breakdown voltage semiconductor device, such as a MOS (a metal-oxide-semiconductor) field effect transistor, and more particularly to a vertical high breakdown voltage semiconductor device which has a superjunction structure and in which a main current flows between two main surfaces of a semiconductor substrate.
B. Description of the Related Art
In the general vertical MOSFET (Metal oxide semiconductor field effect transistor), a high-resistivity n− drift layer has a function of making a drift current flow in the vertical direction (the depth direction of the substrate) in an on state. Therefore, when the current path of the n− drift layer is shortened, that is, when the thickness of the n− drift layer is reduced, drift resistance is reduced, which substantially reduces the on-resistance of the MOSFET.
In an off state, the high-resistivity n− drift layer is depleted to sustain a high breakdown voltage. Therefore, when the thickness of the high-resistivity n− drift layer is too thin, the breakdown voltage becomes low and the depletion layer which is spread from the pn junction between a p base region and an n− drift layer reaches a drain electrode at a low applied voltage. When the high-resistivity n− drift layer is thick, a reverse bias voltage which reaches the critical electrical field strength of silicon (Si) increases. Therefore, a high breakdown voltage semiconductor device is obtained.
However, when the high-resistivity n− drift layer is too thick, the on-resistance increases, which results in an increase in power loss. As such, in the vertical MOSFET, since there is a tradeoff relationship between the specific on-resistance and the breakdown voltage, in general, it is difficult to improve the characteristics of both the specific on-resistance and the breakdown voltage at the same time.
As a device for improving a plurality of semiconductor characteristics having the tradeoff relationship therebetween at the same time, a superjunction semiconductor device has been known which has a superjunction (hereinafter, referred to as SJ) structure in which p-type regions and n-type regions are alternately arranged each other in a drift layer. When the SJ structure is applied to a vertical high-breakdown-voltage semiconductor device, the p-type regions and the n-type regions which extend in the depth direction of the substrate and have a small width are alternately arranged in the n− drift layer in a direction parallel to the main surface of substrate (hereinafter, referred to as a parallel pn layer).
In the parallel pn layer including a plurality of p-type regions and n-type regions, even when each of the p-type region and the n-type region is a region with high impurity concentration, the depletion layer which is spread from the pn junction between all of the regions in the parallel pn layer at a low applied voltage in an off-state has such a small width that both regions are rapidly depleted. Therefore, the parallel pn layer has been known as a structure capable of improving both low on-resistance and high breakdown voltage at the same time. However, in order to obtain high breakdown voltage using the SJ structure in practice, it is important to control the amounts of impurities in the p-type region and the n-type region so as to be as equal as possible.
In addition, in the vertical MOSFET in which the SJ structure is formed in the n− drift layer of the active region in which the main current flows, the configuration of the edge termination region surrounding the active region needs to be different from that of the general power MOSFET. That is, an edge termination region which is appropriately designed so as to maintain a high breakdown voltage is needed in order to increase the breakdown voltage of the MOSFET having the SJ structure. In general, the edge termination region needs to maintain a breakdown voltage higher than that of the active region. Therefore, the SJ structure is formed in the edge termination region. In the edge termination region, when the amount of impurity in the n-type region is not equal to the amount of impurity in the p-type region, the breakdown voltage of the edge termination region is reduced, which leads to a reduction in the breakdown voltage of the high breakdown voltage semiconductor device.
In order to solve this problem, a structure has been known in which the amount of impurity in the parallel pn layer of the edge termination region is half the amount of impurity in the parallel pn layer of the active region (for example, see JP 2000-277726 A and JP 2003-224273 A).
In JP 2000-277726 A and JP 2003-224273 A, in order to set the amount of impurity in the parallel pn layer of the edge termination region to half the amount of impurity in the parallel pn layer of the active region, the dose of impurity ions implanted into the edge termination region may be half the dose of impurity ions implanted into the active region, or the width of an opening formed in a mask for impurity ion implantation in the active region may be half the width of an opening formed in a mask for impurity ion implantation in the edge termination region. For example, as a detailed method of setting the dose of impurity ions implanted into the edge termination region to half the dose of impurity ions implanted into the active region, a method has been proposed in which the implantation of impurity ions are separately performed the number of times impurity ions implanted into the edge termination region is less than the number of times impurity ions implanted into the active region. However, in this case, production efficiency is reduced and costs increase.
The method of setting the width of the opening formed in the mask for impurity ion implantation in the active region to half the width of the opening formed in the mask for impurity ion implantation in the edge termination region can be easily achieved only by changing the width of the opening in the mask. However, a microfabrication process is needed in order to set the width of the opening formed in the mask in the active region to half the width of the opening formed in the mask in the edge termination region. Therefore, in practice, the parallel pn layer in the edge termination region is likely to be affected by a process variation. In addition, a reduction in the width or the pitch between the p-type region and the n-type region in the parallel pn layer is effective in improving a breakdown voltage, but the diffusion (hereinafter, referred to as mutual diffusion) between p-type impurities in the p-type region and n-type impurities in the n-type region increases. As a result, there is a concern that an impurity concentration variation will increase or a parallel pn layer is not formed.
The present invention is directed to overcoming or at least reducing the effects of one or more of the problems set forth above.